1. Field
Apparatuses and methods consistent with the following description relate to an apparatus and method for sharing one or more function logics.
2. Description of the Related Art
A reconfigurable processor generally includes a plurality of functional units and/or a plurality of functional modules, and it is normal that the plurality of functional units commonly perform arithmetic operations and provide output according to a mutually independent given input. However, in some cases of the arithmetic operations, a large function logic of hardware is needed, which may give rise to a difficulty in placing a corresponding arithmetic operation in multiple functional units, in terms of a die size and power consumption, and/or other practical considerations. In a case in which predetermined operations are allocated in a minority of the functional units, because one functional unit performs one arithmetic operation at a time, restrictions can be effectively caused with respect to processing performance for applications that have a plurality of corresponding arithmetic operations. In addition, there is typically a need for routing on a circuit or additional communication that transmits an input to the functional unit which is capable of processing the arithmetic operations for processing the given arithmetic operations and which acquires results. However, if there are not a plurality of the functional units to which the corresponding arithmetic operations are allocated, routing resource efficiency may drop and the performance may decrease, because input/output values must be transmitted very far in many cases. Further, the more routings are increased, the more resource efficiencies are increased, and therefore, scheduling has become increasingly difficult.